SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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Fault model is a model for how faults occur and their impact on circuits. Transistors with channel length less than 3 5 microns are termed as short channel devices.
Critical path is far more complex and optimizations are different compared to adders. Low delay sensitivity to load.
Logic density is less Logic density is higher. Pipelining is a popular design technique often used to accelerate the operation of the data path in digital processors. What is programmable logic array? A device connected so as to pull the output voltage to the lower supply voltage usually 0 V is called pull down device.
EC – VLSI Design TWO MARKS WITH ANSWERS | Manoharan K. –
What is non critical race? What are the various Silicon wafer Preparation?
Contact cut definition 5. No else statement Syntax: These tests assert that all the gates in the chip, acting in concert, achieve a desired function. What are the uses of stick diagram?
Output signal start to change after its input change and settles to the final value within propagation delay. State different types of oxidation. To store ‘1’, it is charged and to store ‘0’ it is discharged to ‘0’ volt. A matrix of programmable interconnect surrounds the basic logic cells. The controllability of an internal circuit node within a chip is a measure of the ease of setting the node to a 1 or 0 state.
What is the difference between mealy and moore state machines? This effect is called substrate bias effect or body effect. Give the different symbols for transmission gate. What are the types of gate arrays in ASIC? One else statement Syntax: What is Enhancement mode transistor?
Methods of timing control: The effective length of the conductive channel is actually modulated by the applied voltage VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.
What is a bit serial multiplier? Click here to sign up. Explain the read and write operations for a one transistor DRAM cell.
It was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity. What are the features of standard celled ASICs? These tests are usually used early in the design cycle to verify the functionality of the circuit.
Logic function is implemented by pull down network only. What is mean by power and power dissipation?
ECVLSI DESIGN 2 MARK QUESTIONS & ANSWERS | Md Ashwaqamer –
This indicates the amount of time after the clock edge, the data input D must be held stable in order for Flip Flop to latch the correct value. What is pass transistor? The threshold voltage VT is not a constant with respect to the voltage difference between the substrate and the source of MOS transistor.
Give the advantages of IC? Named event control 3. Synchronizers are used to reduce metastability. Short-Circuit and Open-Circuit Faults Draw the block diagram gram of serial seria adder.
Verilog supports basic logic gates as predefined primitives. If the channel is initially doped lightly with p type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.
Write the applications of transmission gate? No latch up 2. What are the various shift operations available? Intra-assignment delay control 3. What are the methods available to reduce dynamic power dissipation? In a PAL, the device is programmed by changing the characteristics if the switching element.